Computational Lithography Technology Trends for 32 nm
With each successive technology generation, the computational complexity associated with mask data preparation has increased tremendously. For the 32 nm node, model-based optical proximity correction (OPC) will be applied to nearly all masking levels, and sub resolution assist features (SRAFs) will be used extensively. Additionally, 32 nm will likely drive implementation of double exposure techniques, since depending upon the exact pitch in question, the k1 will drop well below 0.30, making single patterning difficult, if not impossible. This progression has required an evolution in data preparation methods, process model accuracy, simulation methodology, and computational platforms, to meet often competing accuracy and runtime demands.
Polygon processing engines used for design rule checking (DRC) and rule-based OPC can optimally decompose target layouts into two masking levels, depending upon the directives and cost functions employed. Double dipole lithography, for example, requires that the layout be decomposed primarily in terms of horizontal and vertical patterns. Various double patterning schemes including pitch splitting are being explored in early development. At 32 nm, SRAFs will be utilized for the majority of masking layers, and in some cases model-assisted placement will be deployed to mitigate the challenges of complex rule derivation, particularly for contact layers.
Computational Lithography Models
Computational Lithography (CL) models employ a modular approach with mask, optical, resist, and etch components. Vector models accounting for image formation in the photoresist have long been used and the Kirchoff flat mask approximation has been successful for several generations of production OPC. However, at 32 nm the additional accuracy afforded by accounting for the impact of 3D mask topography at highly oblique incidence will be beneficial for immersion applications with polarized illumination (Figure 1).
CD Prediction Error
In addition, newly developed mask manufacturing proximity models will improve wafer OPC accuracy and flexibility through better decoupling of the mask, exposure, and resist processes (Figure 2).
Mask CD Through Pitch
32 nm production will feature increasingly complex illumination sources, and the ability to faithfully render the intensity distribution and predict the imaging response of such sources will be important. Optical fingerprint information contained in the Nikon Scanner Signature File (NSSF), such as longitudinal chromatic aberrations, stage Z moving standard deviation errors, Jones Pupil, and flare will also be utilized to deliver unprecedented accuracy in the OPC and post-OPC verification models. Resist models for OPC have continued to improve in accuracy and predictability, and 32 nm will feature widespread use of etch models accounting for aspect ratio dependent etching and microloading.
Originally, model-based OPC featured “sparse” or polygon-based simulation, where the higher the desired final pattern fidelity to the target, the greater the simulation burden would become. Not surprisingly, as designs shrunk, the number of simulations required for OPC increased. Additionally, it has become necessary to consider process variability during OPC and post-OPC verification.
"Dense" or grid-based simulation was introduced as a more computationally efficient method to generate printing contours. In this method, the entire layout is convolved with the optical and process model kernels in the frequency-domain using Fast Fourier Transform (FFT) techniques, then transformed back to the spatial-domain to predict the printing contour. The net result is that at 45 nm, dense simulation proved to be more computationally efficient than sparse simulation for layers such as metal one and poly. At 32 nm, however, nearly all layers except vias will benefit from reduced runtime in dense versus sparse OPC (Figure 3).
Simulation Runtime Ratio Comparison
Sparse simulation was originally implemented on symmetric multiprocessing (SMP) machines, and later on increasingly large clusters of Linux-based computers. While scaling > 90% can be achieved with this approach, a new computational platform was introduced with Mentor Graphics nmOPC™ and OPCVerify™ at 45 nm. With this technology, various aspects of the simulation and contour generation were ported to the Cell Broadband Engine™, a specialized Co-Processor Accelerator (CPA), which is extremely efficient at FFT Processing. The result is optimal use of existing computer investments along with a small number of CPA processors to reduce OPC runtimes by a factor of 4X or more in most cases, as shown in Figure 3.
Computational Lithography is becoming increasingly vital for advanced technology nodes. 32 nm will feature the introduction of double exposure techniques, and the associated simulation accuracy requirements and data volumes will pose an enormous computational burden. The Calibre™ RET suite of solutions combines an industry-leading polygon processing engine with highly accurate models and cost-effective hardware platforms to meet these challenges.
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